High-Q inductors are a common feature found on most communications semiconductor devices. The most common method of forming an inductor in a semiconductor device involves depositing thick layers, 3 .mu.m or greater, of metal on the top layer of circuitry. This top layer is formed in a spiral pattern in conjunction with a special substrate to create a high-Q inductor. This method has the disadvantage in that to create an inductor of 10, an area of typically more than 300 .mu.m.times.300 .mu.m is required. This area subsequently cannot be used for other circuitry due to electromagnetic interference. Additionally, current processing techniques to form these high-Q inductors that use photoresist and copper require two or more mask levels and two or more exposure steps. This processing results in inductors with air gaps that are not compatible with current processing technology.
Previous attempts have been made at creating lateral high-Q inductors on either non-conducting or highly resistive substrates. However, current chip designs prefer highly conductive substrates for latch-up protection. Current versions of high-Q inductors on silicon substrates have been demonstrated with planar spiral inductors in AlCu, but this technology is not compatible with upper level copper metalization.